FIG. 8 is a circuit diagram of a conventional switched line type phase shifter. In the figure, reference numeral 1 designates an input terminal and reference numeral 2 designates an output terminal. Four field effect transistors 3 are provided at two paths from the input terminal 1 or at the two paths to the output terminal 2 (hereinafter referred to as "FET"). Reference numeral 4 designates resonance lines connected between source and drain electrodes of the FETs 3, respectively, as resonance inductances, respectively. Reference numeral 5 designates gate bias terminals of respective FETs 3. A reference line 6 having a predetermined electrical length .alpha. is provided between the other end of one of the input side FETs 3 and the other end of one of the output side FETs 3. A phase difference producing line 7 having an electrical length (.alpha.+.beta.) which is longer than that of the reference line 6 by a desired electrical length .beta. is provided between the other end of the other one of the input side FETs 3 and the other end of the other one of the output side FETs 3.
Description is given of the operation.
This switched line type phase shifter includes by two single pole double throw switches 50 and 51 which receive signals at the input terminals 1 and 2 and output signals to either of the two output terminals 40a and 40b, 41a and 41b, and two transmission lines 6 and 7 connected between respective output terminals of the one or the other of the two switches, that have electrical length .alpha., (.alpha.+.beta.), respectively. Therefore, by switching the path for the input signal which is input to the input terminal 1 of this phase shifter between that transmitted on the reference line 6 having an electrical length .alpha. to reach the output terminal 2 of this phase shifter, or that transmitted on the transmission line 7 having an electrical length (.alpha.+.beta.) which is longer by a desired electrical length .beta. than the reference line 6, a phase difference .beta. in the electrical length is obtained.
In other words, the switched line type phase shifter shown in FIG. 8 performs a switching operation of the resonance circuit comprising the FETs 3 and the resonance lines 4. When the gate bias voltage of the FETs 3 is set at zero volts, the path between the source and drain electrodes is equivalent to a low resistance of below several .OMEGA., meaning an on-state. When the gate bias voltage of the FET 3 is set below the pinch-off voltage, the path between the source and drain electrodes is equivalent to a parallel circuit comprising a resistance of several k.OMEGA. and a capacitance at off-state (C.sub.T), and having a resonance determined by the off-state capacitance (C.sub.T) and the resonance line 4 connected between the source and the drain of the FET, i.e., an off-state. Even in this off-state, however, it is actually impossible to realize an ideal off-state. Accordingly, a leakage signal is transmitted through the line of the off-state side, and as a result, a signal which is output to the output terminal of the phase shifter is the vector synthesis of the signal transmitted in the on-state line and the leakage signal transmitted in the off-state line. FIG. 9 shows a diagram of this vector synthesization.
In FIG. 9, reference numeral 8 represents a signal vector of a signal transmitted on the reference signal 6. Reference numeral 9 represents a signal vector of a leakage signal transmitted on the line 7. Reference numeral 10 designates a vector obtained by synthesizing the vectors 8 and 9. Reference numeral 11 represents a signal vector of a signal transmitted on the reference line 6. Reference numeral 12 represents a signal vector of a signal transmitted on the line 7. Reference numeral 13 designates a vector obtained by synthesizing the both vectors 8 and 9. In this example, the vector 9 is in an advanced phase relative to the vector 8, the vector 12 is in a retarded phase relative to the vector 11, and the synthesized vector 13 is in an advanced phase by about 90.degree. relative to the synthesized vector 10, presenting this phase difference as the phase shift of this phase shifter.
In this way, in this microwave phase shifter, while the vector 9 is in an advanced phase relative to the vector 8, the vector 12 is in a retarded phase relative to the vector 11, and the electrical length .beta. by which the electrical length (.alpha.+.beta.) of the line 7 is longer than the line 6 is set to a value larger than 90.degree. so that the synthesized vector 13 is at 90.degree. in reverse phase relative to the synthesized vector 10.
In the switched line type phase shifter of such a construction, the amplitudes of the vectors 9 and 12 vary dependent on the variation in the amplitude of the leakage signal of the FET in the off-state and the amplitudes of the vectors 10 and 13 also vary, thereby deviating the angle produced by the synthesized vectors from 90.degree.. Therefore, it is necessary to know the amplitude of the leakage signal in the off-state FET before designing the phase shifter, and it is necessary to adjust the phase shifting by that amount. In this phase shifter, however, when the two FETs located adjacent to each other have the same leakage and the values are not coincident with the design values, the phase shift amount cannot be made 90.degree., and when the off-capacitances FET (C.sub.T) vary between adjacent FETs depending on the non-uniformity of the production process, the amplitude of the leakage signal also varies, thereby varying the phase shift quantity from 90.degree..
The prior art switched line type phase shifter is constituted as described above, and when the off-time capacitance varies dependent on variations in processing, the quantity of signal leaking on the off-side line varies, whereby the synthesized vectors 10 and 13 shown in FIG. 9 vary, resulting in a deviation in the phase shift amount.